Flash technology is widely used e.g. in memory cards, USB drives, MP3 players, and as image storage for digital still cameras. Flash memories are usually based on NAND or on NOR structures. NAND is best suited for flash devices that require high capacity data storage. NAND flash devices usually contain a data register that holds the data e.g. during the so-called programming process, wherein the data are actually written into the flash memory cells.
NAND flash devices usually contain so-called bad blocks or pages, i.e. pages that contain one or more bits that may store no information due to defects and therefore are unusable. Further, NAND flash memories are subject to wear-out, meaning that gradually more and more blocks turn bad. For this and other reasons, blocks may be in a phase where storing data to them is not always successful. For the common NAND flash devices, two specific bounds for the program time are defined in the data sheets: a typical program time and a maximum program time. The typical program time is defined as the time within which more than 50% of all pages are programmed (at a specified voltage level and temperature). Consequently, more than 50% of all page program processes are performed in a time for which the typical program time is the upper bound. For the remaining pages, the maximum program time is the upper bound. E.g. for today's Micron NAND flash devices a typical program time is specified to 300 μs, whereas the maximum program time is specified to 700 μs.
It is the responsibility of the applications that use NAND flash to keep track of such bad blocks. However, good blocks can typically be erased and re-programmed more than 100,000 to 1,000,000 times. The devices programming time decreases slightly with increasing number of write/erase cycles, and the end of life of a device is usually determined by other failures than program failures.
The different typical and maximum program times mentioned above are due to the employed program-verify strategy. This means that multiple attempts to program the data bits are done and verified, until the program process is successful or a time out occurs. This program-verify process is automatically executed by internal control logic.
NAND flash memory has an inherent, non-negligible latency due to the program time that is required to program one page from the data register into the NAND flash cell array. However, the program time for a successful page program process is not fully deterministic, but times are distributed within a range, with the maximum program time as upper bound. Thus, for applications that require data to be stored continuously, the maximum program time determines the effective data rate that can be achieved.
More information on NAND flash technology is available from the “NAND Flash Design Guide” by Toshiba, accessible under www.data-io.com/pdf/NAND/Toshiba/NandDesignGuide.pdf.pdf.